Lateral double diffused metal oxide semiconductor transistors (DMOS) are commonly used in power management integrated circuits (IC) as power transistors which are switched ON or OFF in response to control signals to realize power conversion.
FIG. 1A illustrates a sectional view of a lateral DMOS 100. The lateral DMOS 100 may be formed in a P-type semiconductor substrate 101. The lateral DMOS 100 may further have a N-type drift region 102 formed in the P-type semiconductor substrate 101, a P-type body region 103 in the N-type drift region 102, a source region 104 in the P-type body region 103, a drain region 105 in the N-type drift region 102, a gate region 106 atop a portion of the N-type drift region 102, which is between the source region 104 and the drain region 105, and a source contact 109, a drain contact 110 and a gate contact (not shown in FIG. 1A) respectively contacting the source region 104, the drain region 105, and the gate region 106. An interlayer dielectric layer 111 is provided to prevent shorting between the source contact 109 and the gate region 106, as well as between the drain contact 110 and the gate region 106.
The source region 104 may comprise a heavy doped N-type (N+) region. The drain region 105 may also comprise a heavy doped N-type (N+) region. The gate region 106 may comprise a poly-silicon layer 106A wrapped by an isolation layer 106B. The gate region 106 may cover a portion of the source region 104 and the body region 103, the gate region 106 may also cover a portion of the drain region 105.
Typically, the lateral DMOS 100 may further comprise a heavy doped P-type (P+) region 107 and/or another P-type doped (DP) region 108 having a lower dopant concentration than the P+ region 107. The P+ region 107 may be formed in the source region 104 and the DP region 108 may be formed below the P+ region 107. The P+ region 107 and the DP region 108 are provided to function as a body contact region between the P-type body region 103 and the source contact 109 so as to reduce a resistance of the body region 103 under the source region 104, from the source contact 109 to the end of the source region 104 closest to the gate region 106, thus reducing a base resistance of a parasitic NPN transistor formed by using respectively the N-type drift region 102, the P-type body region 103, and the source region 104 as respectively a collector, a base and an emitter, thereby increasing the ruggedness of the lateral DMOS 100.
Methods and processes of forming the lateral DMOS 100 are well known to those skilled in the art and are not addressed in detail herein. FIG. 1B illustrates a sectional view of a portion of the lateral DMOS 100 to show a source opening 112. The source opening 112 may be formed after the formation of the gate region 106 to expose a portion of the body region 103 so that in the following the source region 104, the P+ region 107 and/or the DP region 108 can be formed in the exposed portion of the body region 103. The source opening 112 shown in FIG. 1B is shared by two neighboring individual lateral DMOS 100 and is confined between two neighboring gate regions 106 of the two neighboring individual lateral DMOS 100. The source opening 112 should have an appropriate size so that the source region 104, the P+ region 107 and/or the DP region 108 and the source contact 109 can be appropriately formed. It can be seen from FIG. 1B that the source opening 112 has a width LS that may be expressed by LS=LCT+2LCT-gate, wherein LCT represents a width of the source contact 109 shared by the two neighboring individual lateral DMOS 100, LCT-gate represents a width from an edge ECT of the source contact 109 to an edge Egate of the gate region 106.
Typically, the source contact 109 should cover both the P+ region 107 and a portion of the N+ source region 104. That is to say, the width LCT of the source contact 109 should be large enough. Moreover, the P+ region 107 has a width that depends on a width of a photoresist layer which is supposed to cover an area where the P+ region 107 is supposed to be formed when forming the N+ source region 104. However, the width of the photoresist layer should not be smaller than a minimum acceptable photoresist width; otherwise the photoresist layer may be deformed or even fall aside. Thus, the width of the P+ region 107 can not be smaller than the minimum acceptable photoresist width, resulting in the width LCT of the source contact 109 being relatively large.
The width LCT-gate should also be large enough at least to ensure that accidental shorting between the source contact 109 and the poly-silicon layer 106A of the gate region 106 should not occur. Further, the width LCT-gate may be expressed by LCT-gate=LCT-DP+LDP-gate, wherein LCT-DP represents a width from the edge ECT of the source contact 109 to an edge EDP of the DP region 108, and LDP-gate represents a width from the edge EDP of the DP region 108 to the edge Egate of the gate region 106. The width LDP-gate should not be too small, because a minimum distance should be kept from the edge EDP of the DP region 108 to the edge Egate of the gate region 106 to ensure that the DP region 108 does not affect a channel threshold of the lateral DMOS 100. Thus, the width LCT-gate may also be relatively large.
In addition, in the process of forming the source region 104, the P+ region 107 and/or the DP region 108 and the source contact 109, at least four photoresist layers and four mask layers should be applied, i.e. a first photoresist layer and a first mask layer for forming the DP region 108; a second photoresist layer and a second mask layer for forming the N+ source region 104; a third photoresist layer and a third mask layer for forming the P+ region 107; and a fourth photoresist layer and a fourth mask layer for forming the source contact 109. The width LCT and the width LCT-gate are directly or indirectly defined by the first, second, third and fourth photoresist layers and mask layers. For each photoresist layer and each mask layer, mask misalignment should be taken into account.
Therefore, for the lateral DMOS 100, the width LS of the source opening 112 may be relatively large, which results in a larger size of the lateral DMOS 100. In addition, at least four photoresist layers and four mask layers should be applied for forming the source region 104, the P+ region 107 and/or the DP region 108 and the source contact 109, and the width LS of the source opening 112 depends on the four photoresist layers and the four mask layers, wherein, for each mask layer, mask misalignment should be taken into account. Thus, the forming of a traditional lateral DMOS 100 could be rather complicated and the cost is high.